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october 2006 rev 2 1/14 14 STP120NF04 n-channel 40v - 0.0047 ? - 120a to-220 stripfet? ii mosfet general features standard threshold drive 100% avalanche tested description this mosfet is the latest development of stmicroelectronics unique ?single feature size?? strip-based process. the resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. applications switching application internal schematic diagram type v dss r ds(on) i d pw STP120NF04 40v <0.0050 ? 120a 300w 1 2 3 to-220 www.st.com order codes part number marking package packaging STP120NF04 p120nf04 to-220 tube
contents STP120NF04 2/14 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STP120NF04 electrical ratings 3/14 1 electrical ratings table 1. absolute maximum ratings symbol parameter value unit v ds drain-source voltage (v gs = 0) 40 v v gs gate-source voltage 20 v i d (1) 1. current limited by package drain current (continuous) at t c = 25c 120 a i d drain current (continuous) at t c = 100c 120 a i dm (2) 2. pulse width limited by safe operating area drain current (pulsed) 480 a p tot total dissipation at t c = 25c 300 w derating factor 2 w/c dv/dt (3) 3. i sd 120 a, di/dt 300 a/s, v dd v (br)dss , t j t jmax. peak diode recovery voltage slope 6 v/ns e as (4) 4. starting t j = 25c, i d = 60a, v dd =30 v single pulse avalanche energy 1.2 j t j t stg operating junction temperature storage temperature -55 to 175 c table 2. thermal data r thj-case thermal resistance junction-case max 0.5 c/w rthj-pcb thermal resistance junction-pcb max see figure 14. on page 8 c/w r thj-a thermal resistance junction-ambient (free air) max 62.5 c/w t l maximum lead temperature for soldering purpose 300 c
electrical characteristics STP120NF04 4/14 2 electrical characteristics (t case =25c unless otherwise specified) table 3. on/off states symbol parameter test cond itions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 40 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating v ds = max rating, t c = 125 c 1 10 a a i gss gate body leakage current (v ds = 0) v gs = 20v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250a 2.8 4.5 v r ds(on) static drain-source on resistance v gs = 10v, i d = 50 a 0.0047 0.0050 ? table 4. dynamic symbol parameter test conditions min. typ. max. unit g fs (1) 1. pulsed: pulse duration=300s, duty cycle 1.5% forward transconductance v ds =15v, i d = 50a 150 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds =25v, f=1 mhz, v gs =0 5100 1300 160 pf pf pf t d(on) t r turn-on delay time rise time v dd = 20 v, i d = 60 a, r g = 4.7 ?, v gs = 10 v (see figure 18) 35 220 ns ns t d(off) t f turn-off delay time fall time v dd = 20 v, i d = 60 a, r g = 4.7 ?, v gs = 10 v (see figure 18) 80 50 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =32v, i d = 120a v gs =10v (see figure 19) 110 35 35 150 nc nc nc
STP120NF04 electrical characteristics 5/14 table 5. source drain diode symbol parameter test conditions min typ. max unit i sd source-drain current 120 a i sdm (1) 1. pulse width limited by safe operating area source-drain current (pulsed) 480 a v sd (2) 2. pulsed: pulse duration=300s, duty cycle 1.5% forward on voltage i sd =120a, v gs =0 1.3 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd =120a, di/dt = 100a/s, v dd =20v, tj=150c (see figure 20) 75 185 5 ns nc a
electrical characteristics STP120NF04 6/14 2.1 electrical characterist ics (curves) figure 1. safe operating area figure 2. thermal impedance figure 3. output characterisics figure 4. transfer characteristics figure 5. transconductance figure 6. static drain-source on resistance
STP120NF04 electrical characteristics 7/14 figure 7. gate charge vs gate-source voltage figure 8. capacitance variation figure 9. normalized gate threshold voltage vs temperature figure 10. normalized b vdss vs temperature figure 11. normalized on resistance vs temperature figure 12. source-drain diode forward characteristics
electrical characteristics STP120NF04 8/14 figure 13. power derating vs tc figure 14. thermal resistance rthj-a vs pcb copper area figure 15. max id current vs tc figure 16. max power dissipation vs pcb copper area
STP120NF04 electrical characteristics 9/14 the previous curve gives the safe operating area for unclamped inductive loads, single pulse or repetitive, under the following conditions: p d(ave) =0.5*(1.3*bv dss *i av ) e as(ar) =p d(ave) *t av where: i av is the allowable current in avalanche p d(ave) is the average power dissipation in avalanche (single pulse) t av is the time in avalanche to derate above 25 c, at fixed i av, the following equation must be applied: i av = 2 * (t jmax - t case ) / (1.3 * bv dss * z th ) where: z th = k * r th is the value coming from normalized thermal response at fixed pulse width equal to t av . figure 17. allowable iav vs time in avalanche
test circuit STP120NF04 10/14 3 test circuit figure 18. switching times test circuit for resistive load figure 19. gate charge test circuit figure 20. test circuit for inductive load switching and diode recovery times figure 21. unclamped inductive load test circuit figure 22. unclamped inductive wavefo rm figure 23. switching time waveform
STP120NF04 package mechanical data 11/14 4 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com
package mechanical data STP120NF04 12/14 dim. mm. inch min. typ max. min. typ. max. a 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 d 15.25 15.75 0.60 0.620 e 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 f 1.23 1.32 0.048 0.052 h1 6.20 6.60 0.244 0.256 j1 2.40 2.72 0.094 0.107 l 13 14 0.511 0.551 l1 3.50 3.93 0.137 0.154 l20 16.40 0.645 l30 28.90 1.137 ?p 3.75 3.85 0.147 0.151 q 2.65 2.95 0.104 0.116 to-220 mechanical data
STP120NF04 revision history 13/14 5 revision history table 6. revision history date revision changes 28-feb-2005 1 first release. 02-oct-2006 2 new template, no content change
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